4 Pin PWM FAN with ATTiny13A

線路圖

PWM 22KHz 確定有輸出

手工藝

洗板子囉

1. LED 三種顯示模式:               

   轉速最慢不亮                       

    轉速最快恆亮                       

    轉速與閃爍成正比              

2. 無段旋鈕調整轉速                

3. 無段旋鈕下壓儲存現在轉速

LED 閃爍三次                  

NIKON S7 鏡頭蓋錯誤 修理

出現傳說中的鏡頭蓋錯誤

明明鏡頭蓋好的很,開電源就打開關電源就合起來

神奇的事出現:讓相機進入待機狀態,然後喚醒,可以用了

大卸八塊,其實是用膠帶把拆下來的螺絲一一黏好,並記錄位置及數量

小心閃光燈的高壓電,連續被電了兩次才知道,這電容用料很實在

看不出壞在哪,鏡頭蓋馬達正常,鏡頭蓋定位開關正常

網路上都說是鏡頭蓋模組故障,買一個來試試,死馬當活馬醫

然後換完後真的就好了,完畢.

利用RU檢查LAN的MAC

INTEL 82574:
1.  MAC_ADDR = ReadPCI32(NIC_BUS, NIC_DEV, NIC_FUN, 0x10);
2.  MAC_ADDR &= (UINT32) (0xFFF00000);
3.  MAC_ADDR  | =(UINT32) 0x40;
4.  MAC_value_offset1 = (UINT8)(MemRead32((UINT32*)(UINT)(MAC_ADDR)));
5.  MAC_value_offset2 = (UINT8)(MemRead32((UINT32*)(UINT)(MAC_ADDR+1)));
6.  MAC_value_offset3 = (UINT8)(MemRead32((UINT32*)(UINT)(MAC_ADDR+2)));
7.  MAC_value_offset4 = (UINT8)(MemRead32((UINT32*)(UINT)(MAC_ADDR+3)));
8.  MAC_value_offset5 = (UINT8)(MemRead32((UINT32*)(UINT)(MAC_ADDR+4)));
9.  MAC_value_offset6 = (UINT8)(MemRead32((UINT32*)(UINT)(MAC_ADDR+5)));

===========================================================
1.Realtek:Io或Memory map offset BYTE[0x00]~BYTE[0x05]
2.Marvell:Memory map offset BYTE[0x100]~BYTE[0x105]
3.SIS:Io map offset  BYTE[0x62]~BYTE[0x67]
4.Intel: Memory map offset  BYTE[0x40]~BYTE[0x45]
5.Broadcom:Memory  map offset  BYTE[0x16b]~BYTE[0x164] 或者 Memory map offset  BYTE[0x1410]~BYTE[0x1415]
6.Jmicron:Memory  map offset  BYTE[0x38]~BYTE[0x3D]

引用自:
http://www.biosren.com/thread-6474-1-1.html

Do not clear the Intruder Detect bit

SBSECInit.asm
SECSB_EarlyInit     PROC PUBLIC
; Disable Auto-Reset Function
        mov     dx, MKF_TCO_BASE_ADDRESS + TCO_IOREG_CNT1
        in      ax, dx
        out     0edh, al                ; I/O delay
        or      ah, 08t                 ; Set Bit[11] to disable TCO timer
        out     dx, ax
        out     0edh, al                ; I/O delay

        mov     dx, MKF_TCO_BASE_ADDRESS + TCO_IOREG_STS2
        in      ax, dx
        out     0edh, al                ; I/O delay
        or      al, 02t                 ; Set Bit[1] to clear SECOND_TO_STS
        and     al, 0FEh                ; Do not clear the Intruder Detect bit ;CN_20110808_JC_02A_01+
        out     dx, ax
        out     0edh, al                ; I/O delay

        mov     esi, MKF_SB_RCRB_BASE_ADDRESS + RCRB_RTC_CONF   ; Enable Upper CMOS
        mov     byte ptr [esi], 04h

        mov     esi, MKF_SB_RCRB_BASE_ADDRESS + RCRB_MMIO_GCS
        mov     byte ptr [esi], 60h or (MKF_RESERVED_PAGE_ROUTE shl 2)

Backup VeB configuration

Tools-> Options->
Tools Directories
Env Variables

Backup Config.dat

Transfer LVDS to HDMI

Intel VGA I.G.D 支援的輸出格式，是以支援標準的輸出格式為主，例如640x480 / 1024x768 / 1280 x 1024…。，。

但是HDMI卻是TV的規格，卻是480i / 720P /1080i /1080p。

所以為了讓PC可以輸出到TV走HDMI，除了硬體的訊號轉換外，還需要修改VGA BIOS。

Intel Standard VGA BIOS雖然不支援1280 x 720的解析度,但是VGA BIOS是可以利用BMP修改的,要修改的是LFP Panel的DTD Timings.

而DTD Timings就是依照VESA EDID的規範做的，要填的有18-Byte。

http://en.wikipedia.org/wiki/Extended_display_identification_data

" The table is the 18-byte DTD structure defined in the VESA EDID version 1.x."

DB ? ; Low Byte of DClk in 10 KHz

DB ? ; High Byte of DClk in 10 KHz

DB ? ; Horizontal Active in pixels, LSB

DB ? ; Horizontal Blanking in pixels, LSB

DB ? ; Bit 7-4: Upper 4 bits of Hor. Active

; Bit 3-0: Upper 4 bits of Hor. Blanking

DB ? ; Vertical Active in lines, LSB

DB ? ; Vertical Blanking in lines, LSB

DB ? ; Bit 7-4: Upper 4 bits of Vert. Active

; Bit 3-0: Upper 4 bits of Vert. Blanking

DB ? ; HSync Offset from Hor. Blanking in pix., LSB

DB ? ; HSync Pulse Width in pixels, LSB

DB ? ; Bit 7-4: Lower 4 bits of VSync Offset

; Bit 3-0: Lower 4 bits of VSync Pulse Width

DB ? ; Bit 7-6: Upper 2 bits of HSync Offset

; Bit 5-4: Upper 2 bits of HSync Pulse Width

; Bit 3-2: Upper 2 bits of VSync Offset

; Bit 1-0: Upper 2 bits of VSync Pulse Width

DB ? ; Horizontal Image Size, LSB

DB ? ; Vertical Image Size, LSB

DB ? ; Bit 7-4: Upper 4 bits of Hor. Image Size

; Bit 3-0: Upper 4 bits of Vert. Image Size

DB 0 ; Horizontal Border in pixels

DB 0 ; Vertical Border in lines

DB ? ; Flags:

; Bit 7: 0 = Non-interlaced, 1 = Interlaced

; Bit 6-5: 00 = Reserved

; Bit 4-3: 11 = Digital Separate

; Bit 2: Vertical Polarity (0 = Negative, 1 = Positive)

; Bit 1: Horizontal Polarity (0 = Negative, 1 = Positive)

; Bit 0: 0 = Reserved

=======================================================================================

DB 01h ; Low Byte of DClk in 10 KHz

DB 1dh ; High Byte of DClk in 10 KHz

;Pixel Clock = Horizontal x Vertical x Frame

;Pixel Clock = 1650 x 750 x 60 = 74.25 MHz

DB 00h ; Horizontal Active in pixels, LSB

DB 72h ; Horizontal Blanking in pixels, LSB

DB 51h ; Bit 7-4: Upper 4 bits of Hor. Active

; Bit 3-0: Upper 4 bits of Hor. Blanking

;Horizontal Active -> 1280 = 0500h

;Horizontal Blanking -> 370 = 0172h

DB D0h ; Vertical Active in lines, LSB

DB 1Eh ; Vertical Blanking in lines, LSB

DB 20h ; Bit 7-4: Upper 4 bits of Vert. Active

; Bit 3-0: Upper 4 bits of Vert. Blanking

;Vertical Active -> 720 = 2D0h

;Vertical Blanking -> 30 = 01Eh

GPIO Generate SCI

GPIO_USE_SEL—GPIO Use Select Register

0 = Signal used as native function.

1 = Signal used as a GPIO.

GP_IO_SEL—GPIO Input/Output Select Register

0 = Output. The corresponding GPIO signal is an output.

1 = Input. The corresponding GPIO signal is an input.

GPI_INV—GPIO Signal Invert Register

0 = The corresponding GPI_STS bit is set when the Chipset detects the state of the input pin to be high.

1 = The corresponding GPI_STS bit is set when the Chipset detects the state of the input pin to be low.

GPIO_ROUT—GPIO Routing Control Register (PM—D31:F0)

GPIOxx Route:

00 = No effect.

01 = SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)

10 = SCI (if corresponding GPE0_EN bit is also set)

11 = Reserved

Scope(\_GPE){

Method (_Lxx,0){

Store(0x15, DBG8) // DBG8 name translates to IO port 80h

Sleep (1000) // Wait for 1sec for display DBG8

}